VoltMatrix: An Analog Computing AI Chip Architecture for Scalable and Energy-Efficient Inference

Overview

Artificial Intelligence (AI) has become a cornerstone of global innovation. However, current digital hardware, such as GPUs, faces critical computational bottlenecks with the growth of next-generation large AI models. These limitations stem largely from excessive power consumption, and thermal constraints restricting chip density and performance growth. Analog computing offers a promising efficient alternative, yet existing pure-analog AI solutions, like memristors, suffer from slow memory updates, noise sensitivity, and fabrication variability, restricting their large-scale viability. This project introduces a novel hybrid analog-digital computing AI chip architecture, incorporating digital control to inherently address pure-analog challenges: data is stored in shift registers, converted to analog voltage and PWM via DAC and timer, and analog switch performs multiplication. The architecture was validated through mathematical modeling, circuit simulations, and experiments with verification PCB prototype. The prototype results demonstrated an average multiplication error of 1.7%, about four times lower than memristors. On the MNIST handwritten digit recognition task, the prototype achieved 94.8% accuracy, indicating its potential for practical applications. Additionally, a near-fabrication chip layout containing 100-multiplication units was designed using the Skywater 180nm process for verification. The layout was simulated at the semiconductor level, which showed approximately three times higher power efficiency than published digital designs with comparable semiconductor process, and twice the accuracy of memristors. Overall, it offers a promising scalable and efficient solution to meet the growing demands of large AI models for fields like robotics, transportation.

Competition history

• ISEF 2025 Embedded Systems · Entry EBED021

Resources

• ISEF abstract page ↗

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