Low-Power Hybrid Analog-Digital Processor for AI Operations

Overview

Neural Networks are intensive, requiring large numbers of Multiplier-Accumulate (MAC) operations, leading to high energy usage for common digital processors. Especially with the growing use of AI, it is important that the hardware utilized can handle the complexity of these models whilst optimizing power usage to best prevent environmental degradation. This project aims to use a hybrid digital-analog approach by using a MOSFET analog crossbar architecture to multiply currents physically to create the values for these MAC operations at a much lower energy cost. To evaluate the method, a PCB demonstration of a single neuron was created and used for inference for the MNIST dataset whilst using an internal shunt resistor to calculate power usage. Later, a digital simulation of this architecture in a 8x8 matrix was created to further analyze power benefits at larger scale. Both of these prototypes function through the use of trans-impedance amplifiers to sum multiple inputted channel currents to receive an output activation voltage. The power saved from the conventional digital method for the PCB neuron was 41.3% with a 2% loss in precision and the power decrease from the digital simulation of the 8x8 crossbar ASIC was 62% when compared to a baseline created. This data demonstrates that this architecture is capable of achieving large power reduction with only minimal losses in the MAC process. In conclusion, this architecture provides both higher accuracy as opposed to pure Analog MAC and higher power-efficiency as opposed to pure Digital methods.