Optimizing Micro-Computer Architecture in the Arithmetic Logic Unit

Overview

Computer processing speed has historically followed a trend of exponential improvement. This phenomenon is explained by Moore’s Law, which states that the number of transistors in a microchip doubles every few years. As the size of transistors decreases, computers become faster and consume less energy. However, transistors are approaching their physical size limit, requiring a new method to improve processing speed. Rather than making the pieces inside the computer smaller, this project optimizes the bit arithmetic algorithms defining processing speed by combining two critical operations in the Arithmetic Logic Unit (ALU), the multiplication and division circuits. Developing the combinational circuit relies on combining the designs of the multiplication and division circuits. Since contemporary multipliers and standard division circuits rely on an adding or subtracting iterative design, many fundamental processes repeat. Innovating an adder/subtractor as the axis of the combinational circuit combines these procedures. The adder/subtractor includes a combination of the CSA and the Two’s Complement, which turns bits negative, so the circuit can add and subtract. The K-value is a single bit acting as the operation code for the demultiplexers to sort through bit pathways and a bit switch for the entire circuit. Modeling the combo circuit in a digital logic simulator, the truth tables for the outputs exactly match the respective multiplication and division solutions. Both operations’ bit pathways overlap significantly, saving the space two circuits would require by replacing dozens of single adders and subtractors with easily switchable functions by 15%. By expanding combinational circuits to encompass more arithmetic functions, the CPU can become substantially faster.

Awards (3)

• Fourth Award of $500 $500
• Air Force Research Laboratory on behalf of the United States Air Force: Glass trophy and USAF medal for each recipient
• Air Force Research Laboratory on behalf of the United States Air Force: First Award of $750 in each Regeneron ISEF Category $750

Competition history

• ISEF 2022 Embedded Systems · Entry EBED012 · Atlanta, Georgia, United States

Resources

• ISEF abstract page ↗

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