Simple-VIII: Designing an 8-bit Computer Architecture for End-to-End Open Source ASIC Implementation

Overview

Modern semiconductors are typically closed-source and lack transparency in design and production. The resulting inability to verify chips allows the introduction of undetectable hardware backdoors at multiple stages. This project evaluates how open silicon can provide verifiable hardware for critical systems. To evaluate, an 8-bit CPU Architecture was developed from scratch. Simulation, verification and synthesis of this system were achieved using only open source tools. Constraining implementation and architecture to enable independent manufacturing, the design was submitted for fabrication on a multi-project wafer. Manufactured hardware was received and evaluated against system simulations. Test vectors were applied and resulting behaviour was observed and compared. The hardware behaviour matched the expected model, providing no evidence of behaviuoral deviation. Results show that silicon developed from open-source logic and with an open process can be verified against its specification independently and transparently without proprietary access. However, verification becomes a limiting factor as system complexity increases. Ongoing work integrates verification logic directly on-chip, drastically reducing the scaling barrier and enabling software-driven verification without exhaustive external testing.

Competition history

• ISEF 2026 Embedded Systems · Entry EBED002

Resources

• ISEF abstract page ↗

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