Motion Detection Algorithm with Hardware Realization

CSEF · 2009 Mathematics & Software

Overview

Objectives/Goals In my project, my objective was to write an algorithm that utilizes a more cost-effective method of detecting motion in image sequences, and then realize this algorithm in FPGA so that the result can be viewed on TV. Methods/Materials In order to detect the area of motion, I will accumulate all the pixel values of each row and column, storing only the summated values. Then, I will compare the summated data of each row and column for the current frame with the previous frame's data by taking the absolute value of the difference between the two values for each row and column. Differences in these values will ultimately allow me to determine where motion has occurred in the image sequence. To complete this project, I need the following programs: Debussy, Modelsim, and Simplify Pro. Other materials include a Xilinx FPGA Chip, Xilinx FPGA tools, an Electronic circuit board with video input/output, a video camera, and a TV. Results When the video camera was connected to the FPGA Development Board after my algorithm had been downloaded into the chip, the output on the TV screen showed white lines surrounding the area in motion, indicating that my algorithm was successful. Conclusions/Discussion My results prove that my algorithm functions, and compared with the original memory sizes needed to store one video frame (from about 338Kbyte of memory to 2Mbyte of memory), the memory required when using my algorithm is small. After summating the pixel values for each frame, I only have 80 rows of data (about 1Kbyte), and 720 columns of data (about 1.5Kbyte) for a 720x480 format. Using my algorithm, the total memory space needed for storage is a mere 2.5 KBytes for 720x480 format, and 7 Kbytes for a 1920x1080 HD video format, a clear cut back in the memory space.

Summary statement

My project is about a more cost-effective method of detecting the area of motion in image sequences.

Help received

Father helped buy FPGA Development Board and briefly assisted with reviewing the algorithm for errors.

Competition history

  • CSEF 2009 Mathematics & Software · Entry S1626

Resources

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