Design and Evaluation of an FPGA-Based Interconnect for Energy-Efficient Data Center Operation

Overview

AI data centers are a growing resource concern because rising electricity demand increases both operating cost and emissions, while cooling infrastructure can also require substantial water use. A major contributor to this footprint is excess capacity kept online to absorb rare but severe traffic spikes. During these high tail-latency periods, the bottleneck is not the server itself, but queueing within the interconnect switches that direct traffic between servers. This project creates a field-programmable gate array (FPGA)-based interconnect platform to reduce queueing-driven tail latency under bursty data center traffic, enabling more efficient operation with less overprovisioning. The system uses multiple custom RP2040-based nodes acting as servers to generate controlled workloads, including incast and synchronized bursts, connected through an FPGA switch implemented on the pico-ice iCE40UP5K platform. An FPGA is well suited to this task because it implements scheduling as custom hardware rather than sequential software, allowing deterministic timing, true parallelism, and direct observation of internal queue behavior. The switch implements a baseline round-robin arbiter and two latency-aware alternatives: oldest-packet-first and deficit round-robin scheduling. For each workload and policy, the platform measures latency distributions, throughput, packet drops, and queue length, then calculates the minimum service capacity required to maintain a fixed p99 latency target. Results show that the best-performing policy reduces the capacity multiplier needed to keep p99 latency below 30 ms from 1.22x to 1.05x, lowering required overprovisioning from 22% to 5%, a 77% reduction in excess headroom.

Awards (2)

• Midwest Microelectronics Consortium: Four cash awards of $3,000 each. $3,000
• Office of Naval Research on behalf of the United States Navy and Marine Corps: The Chief of Naval Research Scholarship Award of $20,000 $20,000

Competition history

• ISEF 2026 Embedded Systems · Entry EBED029

Resources

• ISEF abstract page ↗

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